Model checking techniques have established themselves as significant means in early detection of design errors. When a higher layer protocol is implemented in hardware and we want to verify its implementation satisfying the specification, it cannot be handled by software (protocol) model checking tools as most of these tools are based on an interleaving model unlike the hardware implementations, which are based on a synchronous concurrent model. In this paper, we describe our attempt in modeling and formally verifying the hardware implementation of an ATM ring media access (MAC) protocol using a hardware verification model checking tool, VIS. We succeeded verifying the original asynchronous hardware model of the protocol as well as a synchronous version of it. We also report comparative results of both approaches using VIS and SPIN independently and discuss some abstraction techniques we adopted in the verification.
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