Members

• Murugesh Palanisamy
• Dr. Sofiène Tahar
• Jianping Lu

Description

The project deals with the functional verification of the RCMP (Routing, Cell counting, Monitoring and Policing) Egress Routing Logic using both simulation and model checking . In an ATM network, the RCMP Egress routing logic finds application in a network port interface for an ATM switch fabric. Initially, simulations were done on the available behavioral level VHDL design and the equivalent Verilog design using Synopsys-VSS and Verilog-XL. After that, symbolic model checking was carried out on the BLIF-synthesizable Verilog code using VIS(Verification Interacting with Synthesis) tool. From both simulation and model checking, one design error leading the system to a hang-up state was detected and corrected. The model checking of the Egress logic in VIS was done in a reasonable CPU time.

Publications

1. M. Palanisamy and S. Tahar: Formal Verification of the RCMP Egress Routing Logic; Proc. IEEE 11th International Conference on Microelectronics (ICM'99), Kuwait City, Kuwait, November 1999, pp. 89-92.
2. M. Palanisamy and S. Tahar: RTL Modeling of the RCMP Egress Routing Logic; Proc. IEEE Canadian Conference on Electrical & Computer Engineering (CCECE'99), Edmonton, Alberta, Canada, May 1999, pp. 111-115.
3. M. Palanisamy and S. Tahar: Functional Verification of the RCMP Egress Routing Logic. Technical Report, Concordia University, Department of Electrical and Computer Engineering, September 1998. [14 pages]