Analog circuit design and verification face significant challenges due to circuit complexity and short market windows. In particular, the influence of technology parameters on circuits and issues related to noise modeling and verification still remain a priority for many applications. In this research, we developed an unified methodology for modeling and verification of analog designs in the presence of noise and process variation using run-time verification and pattern matching methods.



Our proposed analog modeling and verification framework is shown in the above figure. We propose an approach based on modeling the noise in analog designs using stochastic differential equations (SDE) in the time domain. Then, we define assertion and statistical verification methods in a MATLAB SDE simulation framework for monitoring properties of interest in order to detect errors. In order to overcome some of the drawbacks associated with monitoring techniques, we define a pattern matching based verification method for qualitative estimation of the simulation traces.

We illustrate the efficiency of the proposed methods on different benchmark circuits. Following are selected peer reviewed publications that highlight our work.

[1] R. Narayanan, I. Seghaier, M. Zaki, and S. Tahar: Statistical Run-Time Verification of Analog Circuits in Presence of Noise and Process Variation; IEEE Transactions on Very Large Scale Integration, Vol. 21, No. 10, October 2013, pp. 1811-1822.

[2] R. Narayanan, A. Daghar, M. H. Zaki and S. Tahar: Using LCSS Algorithm for Circuit Level Verification of Analog Designs, [Proc. IEEE New Circuits and Systems Conference (NEWCAS'12), Montreal, Quebec, Canada, June 2012, pp. 185-188.].

[3] R. Narayanan, M. Zaki, and S. Tahar: Using Stochastic Differential Equation for Verification of Noise in Analog/RF Circuits, Journal of Electronic Testing: Theory and Applications, Vol. 26, No. 1, Springer, February 2010, pp. 97-109

[4] R. Narayanan, A. Daghar, M. H. Zaki and S. Tahar: Verifying Jitter in an Analog and Mixed Signal Design Using Dynamic Time Warping, [Proc. IEEE/ACM Design Automation and Test in Europe (DATE'12), Dresden, Germany, March 2012, pp. 1413-1416.]

[5] R. Narayanan, A. Daghar, M. Zaki, and S. Tahar: Using Pattern Matching for Ensuring Correctness of Oscillator Start-Up Condition; IEEE Frontiers in Analog Circuit (FAC) Synthesis and Verification, 2011.

[6] R. Narayanan, M. Zaki, and S. Tahar: Ensuring Correctness of Analog Circuits in the Presence of Noise and Process Variation Using Pattern Matching, Proc. IEEE/ACM Design Automation and Test in Europe (DATE'11), Grenoble, France, March 2011, pp. 1188-1191

[7] R. Narayanan, M. Zaki, B. Akbarpour, S. Tahar, and L. Paulson: Formal Verification of Analog/RF Circuits in the Presence of Noise and Process Variation; Proc. IEEE/ACM Design Automation and Test in Europe (DATE'10), Dresden, Germany, March 2010, pp. 1309-1312

[8] Z. Wang, N. Abbasi, R. Narayanan, G. Al Sammane, M. Zaki, and S. Tahar: Verification of Analog and Mixed Signal Designs using Online Monitoring, Proc. IEEE International Mixed-Signals, Sensors, and Systems Test Workshop (IMS3TW'09), Scottsdale, Arizona, USA, June 2009, pp. 1-8

[9] R. Narayanan, G. Al Sammane, M. Zaki, and S. Tahar: Using Stochastic Differential Equation for Assertion Based Verification of Noise in Analog/RF Circuits, Proc. IEEE International Mixed-Signals, Sensors, and Systems Test Workshop (IMS3TW'09), Scottsdale, Arizona, USA, June 2009, pp. 1-8

[10] R. Narayanan, N. Abbasi, M. Zaki, G. Al Sammane, and S. Tahar: On the Simulation Performance of Contemporary AMS Hardware Description Languages, Proc. IEEE International Conference on Microelectronics (ICM'08), Sharjah, UAE, December 2008, pp. 390-393

[11] R. Narayanan, N. Abbasi, M. Zaki, G. Al Sammane, and S. Tahar: A Comparative Study of AMS Circuit Simulation in VHDL-AMS and SystemC-AMS, International Conference on Embedded Systems & Critical Applications (ICESA'08), pp.23-28, May 2008.