Technical Report
On
the Simulation Performance of Contemporary AMS Hardware Description Languages.
Rajeev
Narayanan, Naeem Abbasi, Mohammed Zaki, Ghiath Al Sammane, and Sofi`ene Tahar
ABSTRACT
Mixed-Signal
extensions to VHDL, Verilog, and SystemC languages have been developed in order
to provide a unifying environment for the modeling and verification of Analog
and Mixed Signal (AMS) designs at different levels of abstraction. In this paper,
we model the behavior of a set of benchmark designs in VHDL-AMS, Verilog-AMS
and SystemC-AMS and compare the simulation performance with HSPICE. The various
experimental results observed for the benchmark circuits show the superiority of
VHDL-AMS and Verilog-AMS against SystemC-AMS and SPICE in terms of simulation
run-times at lower level of abstraction.
|
|
|
|
