The project deals with the functional verification of the RCMP Egress Routing Logic using both simulation and model checking . In an ATM network, the RCMP Egress routing logic finds application in a network port interface for an ATM switch fabric. Initially, simulations were done on the available behavioural level VHDL design and the equivalent Verilog design using Synopsys-VSS and Verilog-XL. After that, symbolic model checking was carried out on the BLIF-synthesizable Verilog code using VIS(Verification Interacting with Synthesis) tool. From both simulation and model checking, one design error leading the system to a hang-up state was detected and corrected. The model checking of the Egress logic in VIS was done in a reasonable CPU time.

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Download Egress in VHDL (VHDL Code)

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