The project aims at designing a floating-point exponential function using the table-driven method. The algorithm was first implemented using sequential VHDL and later translated to concurrent Verilog. The main part of the project consisted of creating modules that would handle basic IEEE-754 single precision number manipulation routines such as addition, multiplication, and rounding to nearest integer. Using these routines, a model was implemented using the described algorithm. The VHDL design, as well as the Verilog design, were simulated and the results proved to be satisfactory.

Download postscript file (PS File)

Download VHDL (VHDL Code)

Download Verilog source code (Verilog Code)

Send comments and suggestions to: tahar@ece.concordia.ca