Technical Report

 Formalization of Cadence SPW Fixed-Point Arithmetic in HOL

Behzad Akbarpour, Sofiène Tahar and Abdelkader Dekdouk  

ABSTRACT


In this report we propose the formalization in higher-order logic of fixed-point arithmetic based on the SPW (Signal Processing WorkSystem) tool. We encoded the fixed-point number system and specified the different rounding modes in fixed-point arithmetic such as the directed and even rounding modes. We also considered the formalization of exceptions detection and their handling like overflow and invalid operation. An error analysis is then performed to check the correctness of the rounding and to verify the basic arithmetic operations, addition, subtraction, multiplication and division against their mathematical counterparts. Finally, we showed by an example how this formalization can be used  to enable the verification of the transition from the floating-point to fixed-point algorithmic levels in the design flow of signal processors.
 
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Send comments and suggestions to: behzad@ece.concordia.ca