Technical Report

Run-Time Hypothesis Testing of Analog Circuits in Presence of Noise and Process Variations

Rajeev Narayanan, Mohamed H. Zaki and Sofiene Tahar


Today's analog/RF design and verification face significant challenges due to circuit complexity and short market windows. In particular, the influence of technology parameters on circuits, and the issues related to noise modeling and verification still remain a priority for many applications. Noise could be due to unwanted interaction between the circuit elements or it could be inherited from the circuit elements. In addition, manufacturing disparity influence the characteristic behavior of the manufactured circuits. In this report, we discuss a methodology for modeling and verification of analog/RF designs in the presence of noise and process variation using statistical run-time verification technique. In order to study the statistical behavior of noise, our approach is based on modeling the designs using stochastic differential equations (SDE), an extension to ordinary differential equations (ODE) with stochastic properties that are suited for modeling a continuous systems in time domain. Then, we define a run-time based verification method combined with process variation, integrated in the SDE simulation framework for monitoring properties of interest in order to quickly detect errors. PDF file (PDF File) comments and suggestions to: Rajeev Narayanan