Technical Report

Modeling and Verification of Embedded Systems using Cadence SMV

Ali Abbas Mir, Subhashini Balakrishnan and Sofiene Tahar


Embedded systems are becoming increasingly popular due to their widespread applications.  With formal verification we verify that every possible behavior of the target system satisfies the specification. SMV is a formal verification system for hardware designs, based on a technique called "symbolic model checking".  In this report we investigate the modeling and verification of an embedded system using Cadence SMV. We constructed a Verilog model of the system by integrating the microcontroller RT level and the embedded software assembly code level. We then validate our models and verification by conducting model checking which analyzes essential aspect of the target embedded system.

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