System-on-chip Verification project

Hardware verification group

Technical Report

Transaction level modeling allows exploring several SoC design architectures leading to better performance and easier verification of the final product. In this report, we present an approach to design and verify SystemC models at the transaction level. We integrate the verification as part of the design-flow where we first model both the design and the properties (written in PSL) in UML; then, we translate them into an intermediate format modeled with AsmL (language based on Abstract State Machines (ASM)). The AsmL model is used to generate an FSM of the design including the properties. Finally, we translate the verified design to SystemC and map the properties to a set of assertions (as monitors in C#) that can be reused to validate the design at lower levels by simulation. At the SystemC level, we also present a genetic algorithm to enhance the assertions coverage. We will ensure the soundness of our approach by proving the correctness of the SystemC to AsmL and AsmL to SystemC transformations. We illustrate our approach on two case studies including the PCI bus standard and a Master/ Slave generic architecture from the SystemC library.

Design and Verification of SystemC Transaction Level Models

A. Habibi and S. Tahar

Date: December 2004

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