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Description
For our best of knowledge, all the current verification tools and languages for System on Chip SoC, use a random test generator that does not achieve a high coverage rate.
HVG (Dr. Habibi and Tahar) proposed a new approach for assertion based verification ABV of SoC. They used a layer of Property Specification Language PSL or System Verilog Assertion SVA on the top of the SystemC library. They introduced the using of genetic algorithm as a better method to generate test vectors than the random ones, and it showed an improvement of factor eight in the coverage metric.
Currently, we are working on a case study to generate test vectors for Look-Aside Interface LA-1 using manually optimized classical genetic algorithm. At the moment, we ignore the addition of assertion layer on the top of SystemC library, and we are writing the required assertion using SystemC semantics.
Specman and E-language is a well know tool from Verisity for verification purpose and its integrated to support Verilog language.
For comparison purpose, we convert our SystemC design to a Verilog design, and our GA-based test generator to a Verilog module, so we can compare the coverage results of Specman tool and our Verilog converted GA-based test generator.
Our final target is to optimize the genetic algorithm for that purpose, and use another ideas from the evolutionary programming EP and artificial life AL like cooperative and competitive evolution and dynamic fitness function. This will give us a better coverage rate, and will make our verification methodology more suitable for verification of huge SoC design, and all of that using single environment (SystemC/ C++..)
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