Functional Coverage Analysis using Stochastic Process based on Different Probability Distribution Function



  • Essam Ahmed
  • Sofiène Tahar
  • Ali Habibi


Functional verification plays an important role in hardware design and verification cycle due to the increasing complexity of hardware design. The main challenging concern in functional verification is finding suitable test vectors that can provide high coverage rate.

HVG (Dr. Habibi and Tahar) proposed a new approach for assertion based verification ABV of SoC. They used a layer of Property Specification Language PSL or System Verilog Assertion SVA on the top of the SystemC library. They introduced the using of genetic algorithm as a better method to generate test vectors than the random ones, and it showed an improvement of factor eight in the coverage metric.

Coverage verification allows to modify the directives of the test generator and target the area of the design that are not covered. This process of adapting the directive of test generator according to feedback based on coverage report is called Coverage Directed Test Generation (CDG). CDG is manual and exhausting process but it is vital to complete the verification cycle.

Attempts are made to automate the verification cycle by applying different Artificial intelligent techniques such as Bayesian network, Neural Network and Genetic Algorithm [1][2][3]. To increase the coverage of multiple coverage points and targeting complex coverage task while achieving high coverage rate a Cell-based Genetic Algorithm (CGA) is developed to automate CDG [1].

For comparison purpose, we convert our SystemC design to a Verilog design, and our GA-based test generator to a Verilog module, so we can compare the coverage results of Specman tool and our Verilog converted GA-based test generator.

We propose further enhancement to CGA by using different probability distribution functions (pdf) such as Normal (Gaussian) distribution, Exponential distribution, Gamma distribution, Beta distribution and Triangle distribution for random number generator and apply the modified algorithm to more complex hardware design at the system level with large number of coverage points.

propoed framework


Concordia University