Alongside Qualcomm, ST Microelectronics, Intel, Synopsys and other top EDA companies and academic research groups, the Hardware Verification Group (HVG) at Concordia University proposed an innovative approach to enable the verification of SystemC using a combination of different techniques: simulation, model checking, assertion based verification and theorem proving. While most people work on SystemC from a hardware background and approach it from that angle, with a focus pure simulation as verification means, Concordia's HVG is considering the design as one system described in one language, SystemC, that can be analyzed and verified as a whole.

The principle behind this approach resides in the conversion of the SystemC and PSL into Abstract State Machines language (AsmL), which can be checked and tested by powerful tools including model checkers, theorem provers and simulators. Assertions and properties, given in the PSL (Property Specification Language) standard, can also be easily compiled to C or C# code. The goal of our endeavor is to offer a complete framework for the analysis and verification of SoCs modeled in SystemC starting from high level requirements descriptions (e.g., in UML) to a final hardware/software design product.

These new SOC test challenges must be solved, while keeping the testing time and volume of test data under control. The focus of the digital SOC testing project is to better understand the impact of emerging design methods on the test flow, and to develop new embedded logic architectures and computer-aided design algorithms for test planning, generation and application that can be used for detecting the faulty components, for speed binning and for discovering the sources of systemic and random failures. This will ultimately improve screening of fabrication defects at a lower cost, as well as accelerate the manufacturing yield learning.