Large analog circuit models are very expensive to evaluate and verify. New techniques are needed to shorten time-to-market and to reduce the cost of producing a correct analog integrated circuit. Model order reduction is an approach used to reduce the computational complexity of the mathematical model of a dynamical system, while capturing its main features. This technique can be used to reduce an analog circuit model while retaining its realistic behavior. We propose a framework for enhacing the behavioral verification of nonlinear analog circuit using model order reduction, as shown in the following figure.





We provide first a modeling environment based on modified nodal analysis and curve-fitting, where analog circuit diffferential models are automatically generated using SPICE netlist and simulation traces. The uncertainties about the initial conditions, parameter and inputs are incorporated in their differential models as fuzzy numbers. Then, the obtained fuzzy differential models are solved using a qualitative simulation method that characterizes their behavior and provides a means to characterize their behavioral properties. Then, we use different techniques such as state space clustering, linearization, and Krylov space projections within an iterative process that ends with the satisfaction of a set of conformance criteria which guarantee the effciency of the reduced model in terms of accuracy and speed-up. We also employ the model order reduction method to speed-up statistical simulation by reducing the size of all the models which are usually simulated in a Monte Carlo context. The application of this work in various large analog circuits proves the effectiveness of our approaches.

Publications

Journal Papers

H. Aridhi, M. H. Zaki and S. Tahar: Enhancing Model Order Reduction for Nonlinear Analog Circuits Simulation [Preliminary Version Accepted for Publication at IEEE TVLSI Journal on March 19th, 2015]

Conference Papers

O. Lahiouel, H. Aridhi, M. H. Zaki, and S. Tahar: Enabling the DC Solutions Characterization using a Fuzzy Approach[Proc. IEEE New Circuits and Systems Conference (NEWCAS'14), Trois-Rivières, Quebec, Canada, June 2014, pp. 161-164.]

P. Winkler, H. Aridhi, M. H. Zaki, and S. Tahar: Generation of Reduced Analog Circuit Models Using Transient Simulation Traces [Proc. Great Lakes Symposium on VLSI (GLSVLSI'14), Houston, Texas, USA, May 2014, pp. 305-310.]

I. Seghaier, H. Aridhi, M. H. Zaki, and S. Tahar: A Qualitative Simulation Approach for Verifying PLL Locking Property [Proc. Great Lakes Symposium on VLSI (GLSVLSI'14), Houston, Texas, USA, May 2014, pp. 317-322.]

O. Lahiouel, H. Aridhi, M. H. Zaki, and S. Tahar: A Semi-Formal Approach for Analog Circuits Behavioral Properties Verification [Proc. Great Lakes Symposium on VLSI (GLSVLSI'14), Houston, Texas, USA, May 2014, pp. 247-248.]

H. Aridhi, M. H. Zaki and S. Tahar: Towards Improving Simulation of Analog Circuits Using Model Order Reduction [Proc. IEEE/ACM Design Automation and Test in Europe (DATE'12), Dresden, Germany, March 2012, pp. 1337-1342.]

Technical Reports

P. Winkler, H. Aridhi, M. H. Zaki, and S. Tahar : Model Order Reduction using SPICE Simulation Traces

O. Lahiouel, H. Aridhi, M. H. Zaki, and S. Tahar: A Tool for Modeling and Analysis of Analog Circuits

Matlab Codes

Readme File

Matlab Codes