Circuit sizing consists in determining the device sizes and biasing voltages and currents such that the circuit satisfies its specifications. In this project, we propose a framework for enhancing analog circuit sizing in the presence of pocess variation. We use Satisfiability Modulo Theory (SMT) solving techniques to exhaustively explore the design search space and compute a continuous set of feasible design solutions. Next, the yield optimization stage determines the most robust design solution (i.e., with the highest yield rate). The optimization block employs a global and a local optimization phases. Moreover, a surrogate-based yield estimation is proposed. The method characterizes the failure regions as a collection of hyperrectangles in the parameters space. The yield computation is based on a geometric calculation of probabilistic volumes subtended by the located hyperrectangles. The application of this work on various analog circuits shows that our approach can achieve higher quality in analog synthesis and unrivaled coverage of the analog design space.

Publications

Journal Papers

O. Lahiouel, M. H. Zaki, and S. Tahar: Accelerated and Reliable Analog Circuits Yield Analysis using SMT Solving Techniques; IEEE Transactions on CAD of Integrated Circuits and Systems, DOI: 10.1109/TCAD.2017.2651807, January 2017, pp. 1-14.

Conference Papers

O. Lahiouel, M. H. Zaki, and S. Tahar: Enhancing Analog Yield Optimization for Variation-aware Circuits Sizing, Design Automation and Test in Europe (DATE'17), to appear, 2017

O. Lahiouel, M. H. Zaki, and S. Tahar: A Framework for Variation-Aware Analog Circuits Sizing, Design Automation and Test in Europe (DATE'17), University Booth, to appear, 2017

O. Lahiouel, M. H. Zaki, and S. Tahar: Towards Enhancing Analog Circuits Sizing using SMT-based Techniques[Proc. Design Automation Conference (DAC '15), San Francisco, California, USA, June 2015, pp. 1-6]

Matlab Codes

Readme File

Matlab Codes